1. Technical Field
The present invention relates in general to the field of integrated circuits and, in particular, to circuit design methodology and tools. More particularly, the present invention relates to a method for reducing the effect of wearout mechanisms on signal skew in the design of an integrated circuit.
2. Description of the Related Art
Electronic devices, such as application-specific integrated circuits (ASICs), processors, memory components, controllers, signal converters, and other integrated circuits (ICs) are commonly found in electronic systems such as desktop, mobile, and hand-held computers. These electronic devices contain storage circuits, such as latches, flip-flops, and registers, that are connected to each other by signal lines that enable one storage circuit to communicate with another. Signal lines carry different types of signals such as data and clock signals. A logic signal line carries data signals, including, for example, address, data, or control information, and a clock signal line carries clock signals. A clock signal is a signal that controls the operation of a circuit by synchronizing the time intervals during which data signals can be communicated from one storage circuit to another.
It is important that a data signal from a first storage circuit to a second, sequential storage circuit, traveling along a data signal line, is delayed long enough to ensure that the data signal does not reach the second storage circuit before the clock signal to the second storage circuit properly gates the data signal at the input to the second storage circuit. Otherwise, data may be lost. Delay on the data signal line is increased by, for example, inverters, logic gates, or other buffers on the data signal line that impede the path of the data signal communicated along the data signal line.
It is important that the design of elements placed on the data signal line cause a delay on the data signal that is more than the minimum amount of time that is necessary to preserve data integrity and less then the maximum time prior to a setup violation. In addition, the speed of communication between the two sequential storage circuits should not be unduly slowed by over-compensating for setup and hold, potentially slowing the speed of the electronic device. It is the job of the circuit designer to verify proper communication between two sequential storage circuits by ensuring that the data signal on the data signal line between the two storage circuits is designed with adequate setup and hold times. However, this verification is typically done during circuit simulations, before the electronic device is actually manufactured. Unfortunately, because this verification is done during simulation, the exact amount of delay that is necessary to ensure proper communication between two circuits cannot be known, and is therefore estimated based on the layout of the circuit, the frequency of the clock, the manufacturing process, and other factors. Because of these margins for error in the simulation, designers will often design in a margin, or xe2x80x9cguard-band,xe2x80x9d to the timing parameter of the design.
Within an integrated circuit, the clock signal, also known as a xe2x80x9cglobalxe2x80x9d clock signal, is used to synchronize data operations performed by elements positioned at different locations on the chip. For example, an element at one location may indicate that information will be available in an internal register during the next global clock cycle. By using the same global clock signal, an element at another location may read the information from the register at the appropriate time. With each new process generation, the frequency of the global clock signal has also increased.
The performance of an IC is based, at least in part, on the synchronization of the global clock signal throughout the chip. Clock skew, the difference in arrival time of the clock signal to various clocked elements, limits the performance of the design. For example, it is desirable that information stored in a register is not read before the information has been correctly updated. Moreover, waiting too long before reading the information will usually slow down the operation of the IC. Thus, it is desirable to have the global clock signal arrive at different locations, or destinations, as close to simultaneously as possible.
A number of factors may cause the global clock signal to be skewed at different locations on the chip. For example, variations in the effective channel length of devices across the chip may occur because of in-die variations resulting from lens distortion, wafer planarity or stepper accuracy. Local effects, like device proximity, may also result in variations in channel length. Supply voltage variations across the chip may likewise cause skew, depending on the power grid design and proximity to high activity or large devices. Moreover, Inter-Layer Dielectric (ILD) thickness variation, causing variations in interconnect capacitance, and signal coupling to neighboring lines, may result in delay variation. Also, a un-modeled effects or deficiencies in the modeling may also contribute to skew.
As will also be appreciated by those skilled in the art, the detrimental effect of clock skew may force the designer to similarly reduce the effective clock period for setup times in certain logic paths within the design, and thus may reduce the performance of the design. For high performance designs that have strict timing requirements, clock skew may consume a substantial portion of the total clock period available for signal setup and this must also be carefully controlled by the designer.
Therefore, one goal of clock tree design is to minimize clock skew. Clock skew is present because of both design skew and process skew. Design skew results from a clock tree design that is not optimal. Different portions of the clock tree may have different loads, or signal routes may not be exactly the same length. Process skew results from the manufacturing process used to make the die. Across-chip variation in line-widths and implant doses can cause otherwise identical circuits to act differently depending on their position on a chip. The total clock skew of the design is the sum of these two components. Clock skew is managed as part of the chip design, and a clock skew budget is usually created. Once the design skew is known and the process skew is estimated, the clock skew of the design can be compared to the clock skew budget. Alternatively, the clock tree can be designed with minimum clock skew and the performance of the chip is then xe2x80x9csetxe2x80x9d given the actual clock skew achieved. If the actual skew of the design is worse than the skew that was assumed during the design of the chip, the design may not function. Likewise, if the actual skew is less than the skew that was assumed during the design of the chip, the design will not be operating up to its full potential.
One factor further complicating this design problem is the current trend in semiconductor design to allow clock gating (make inactive during periods of non-use) of clock trees and other circuits as means of reducing power requirements. As the number of circuits that can be placed on a die increases, and the frequency of operation increases, the power requirements of the die increases. In order to prolong battery life or in order to be able to use simpler packaging solutions, semiconductor designers must find ways of lowering on-chip power. One method of doing this is gated clock trees. When a clock tree is gated, it does not propagate the clock signal and therefore clocked devices do not switch, saving active power.
With the use of clock gating, different frequencies of use of data paths, different numbers of delay elements introduced along data paths between registers, use of different circuits to perform similar functions, input skews, and different loading on the same circuit, all can contribute an additional component of skew due to the variable effects of device wearout mechanisms on each of the different circuits across the chip. In particular, every circuit on a chip is subject to wearout mechanisms, two of which are NBTI (negative bias threshold instability) and hot electrons. These mechanisms cause changes to occur in individual transistors. These changes are a function of how the transistor is used as a function of time. When a circuit is gated, as in clock tree gating, the circuit undergoes different xe2x80x9cagingxe2x80x9d than a circuit that is not gated. This difference in aging, in the context of gated clock trees, can result in additional clock skew. This additional skew, due to difference in use between two otherwise identical circuits, causes the performance of the design to be lower than would be obtained had the gating not been present. Alternatively, if the skew due to gating is not accounted for when the initial design was completed, the chip could fail to function at some point later in time due to the additional skew caused by the clock gating.
Several methods of reducing global clock skew are well-known. For example, designers strive to reduce the part of the path that is different between two clock signals. Because each portion, or xe2x80x9cstage,xe2x80x9d which is different may contribute to the clock skew, reducing the number of stages which are different may reduce the clock inaccuracy. Clocks which are logically the same may also be tied together when they are physically close, and a common node is no more than two or three stages back. Additionally, attempts have been made to reduce signal coupling to clock lines, but this generally involves increased line spacing or the insertion of shielding wires. All of these solutions have become less effective with the increase in IC clock frequency. Moreover, the methods have become more difficult because the number of elements in a single IC has increased dramatically over the years. Most importantly, these prior art methods do not take into account the degradation of signal skew due to wearout mechanisms.
In view of the foregoing, a need exists for a method for reducing the effects of skew degradation over the lifetime of a part to improve synchronization within an integrated circuit, and solving the other problems discussed above.
To address the above and other shortcomings in the art, the present invention provides a method for designing an integrated circuit containing a clock tree or memory, that accounts for the asymmetric shift in performance between different circuits over the lifetime of the integrated circuit due to wearout mechanisms, such as NBTI and hot-e effects. An improvement of half of the portion of skew due to wearout mechanisms can be obtained.
Therefore, in accordance with the present invention, a method for reducing the effect of signal skew degradation in the design of an integrated circuit is provided. First, a circuit design library is created describing library cells as a function of one or more environmental variable, wherein the one or more environmental variable includes a skew degradation variable indicating skew degradation of a signal as a function of a total number of signal switches of the signal. Then, the integrated circuit design is modeled utilizing the circuit design library to determine a first skew degradation for each of the first and second signals at a first predetermined number of signal switches, and a second skew degradation for each of the first and second signals for a second predetermined number of signal switches, and further to determine a first relative skew degradation for a first predetermined number of signal switches and a second relative skew degradation for a second predetermined number of signal switches, wherein a relative skew degradation is equal to the difference of the skew degradation of the first signal and the skew degradation of the second signal for a given number of signal switches. Next, a skew shift equal to the difference between the first relative skew degradation and the second relative skew degradation is calculated. Finally, the integrated circuit design is modified such that a skew degradation of the first signal at the first predetermined number of signal switches is determined to be equal to the first skew degradation of the first signal minus half of the skew shift.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.